000			01844cam a2200361 a 4500
001			14469713
003			ZET-ke
005			20220322113834.0
008			060727s2007 ne a b 001 0 eng
010			_a 2006024358
020			_a0123704901 (pbk. : alk. paper)
020			_a9780123704900
035			_a(OCoLC)ocm70830951
035			_a(OCoLC)70830951
040			_aDLC _cZET-ke _dBAKER _dC#P _dYDXCP _dDLC
050	0	0	_aQA76.9.A73 _bH46 2007
082	0	0	_a004.2/2 _222
100	1		_aHennessy, John L.
245	1	0	_aComputer architecture : _ba quantitative approach / _cJohn L. Hennessy, David A. Patterson ; with contributions by Andrea C. Arpaci-Dusseau ... [et al.].
250			_a4th ed.
260			_aAmsterdam ; _aBoston : _bMorgan Kaufmann, _c2007.
300			_axzvii, 673p. : _bill. ; _c24 cm. + _e1 CD-ROM (4 3/4 in.)
504			_aIncludes bibliographical references and index.
505			_aFundamentals of computer design -- Instruction-level parallelism and its exploitation -- Limits on instructional-level parallelism -- Multiprocessors and thread-level parallelism -- Memory hierarchy design -- Storage systems -- Pipelining: basic and intermediate concepts -- Instructional set principles and examples --Review of memory hierarchy.
650		0	_aComputer architecture. _91384
700	1		_aPatterson, David A.
700	1		_aArpaci-Dusseau, Andrea C.
856	4	1	_3Table of contents only _uhttp://www.loc.gov/catdir/toc/ecip0618/2006024358.html
856	4	2	_3Publisher description _uhttp://www.loc.gov/catdir/enhancements/fy0665/2006024358-d.html
906			_a7 _bcbc _corignew _d1 _eecip _f20 _gy-gencatlg
942			_2lcc _cBK _hQA76.9.A73 _iH46 2007 _kQA76.9.A73 _mH46 2007
999			_c5130 _d5130