| 000 | 01273cam a2200313 a 4500 | ||
|---|---|---|---|
| 001 | 14628284 | ||
| 003 | ZET-ke | ||
| 005 | 20220427172859.0 | ||
| 008 | 061108s2007 flua 001 0 eng | ||
| 010 | _a 2006052725 | ||
| 020 | _a9781420051544 | ||
| 035 | _a(OCoLC)ocm76263541 | ||
| 035 | _a(OCoLC)76263541 | ||
| 040 |
_aDLC _cDLC _dBAKER _dBTCTA _dC#P _dYDXCP _dDLC |
||
| 050 | 0 | 0 |
_aTK7868.D5 _b.C38 2007 |
| 082 | 0 | 0 |
_a621.39/2 _222 |
| 100 | 1 | _aCavanagh, Joseph. | |
| 245 | 1 | 0 |
_aVerilog HDL : _bdigital design and modeling / _cJoseph Cavanagh. |
| 260 |
_aBoca Raton, FL : _bCRC Press, _cc2007. |
||
| 300 |
_axviii, 900 p. : _bill. ; _c26 cm. |
||
| 500 | _aIncludes index. | ||
| 505 | _aIntroduction -- Language elements -- Expressions -- Gate- Level modeling -- User-defined primitives -- dataflow modeling -- Tasks and functions -- Additional design examples | ||
| 650 | 0 |
_aDigital electronics. _91907 |
|
| 650 | 0 |
_aLogic circuits _xComputer-aided design. |
|
| 650 | 0 | _aVerilog (Computer hardware description language) | |
| 856 | 4 | 2 |
_3Publisher description _uhttp://www.loc.gov/catdir/enhancements/fy0626/2006052725-d.html |
| 906 |
_a7 _bcbc _corignew _d1 _eocip _f20 _gy-gencatlg |
||
| 942 |
_2lcc _cBK _hTK7868.D5 _i.C38 2007 _kTK7868.D5 _m.C38 2007 |
||
| 999 |
_c5234 _d5234 |
||